479.575 PEOPLE
| People | Locations | Statistics |
|---|---|---|
| Ziakopoulos, Apostolos | Athens |
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| Vigliani, Alessandro | Turin |
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| Catani, Jacopo | Rome |
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| Statheros, Thomas | Stevenage |
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| Utriainen, Roni | Tampere |
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| Guglieri, Giorgio | Turin |
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| Martínez Sánchez, Joaquín |
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| Tobolar, Jakub |
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| Volodarets, M. |
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| Piwowar, Piotr |
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| Tennoy, Aud | Oslo |
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| Matos, Ana Rita |
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| Cicevic, Svetlana |
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| Sommer, Carsten | Kassel |
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| Liu, Meiqi |
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| Pirdavani, Ali | Hasselt |
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| Niklaß, Malte |
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| Lima, Pedro | Braga |
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| Turunen, Anu W. |
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| Antunes, Carlos Henggeler |
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| Krasnov, Oleg A. |
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| Lopes, Joao P. |
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| Turan, Osman |
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| Lučanin, Vojkan | Belgrade |
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| Tanaskovic, Jovan |
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Valero, M.
in Cooperation with on an Cooperation-Score of 37%
Topics
- estimate
- abstract
- accounting
- coding system
- voltage
- low voltage
- design
- architecture
- filament
- data
- data management
- safety
- algorithm
- real time control
- interference
- behavior
- temperature
- billing
- quantitative analysis
- noise
- workload
- re-procurement
- control device
- resource allocation
- scheduling
- forecasting
- optimisation
- software
- computer operating system
- queuing
- implementation
- shopping facility
- neural network
- embedded system
- show 4 more
Publications (67/67 displayed)
- 2017SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems
- 2016DReAM: An approach to estimate per-task DRAM energy in multicore systemscitations
- 2015Sensible energy accounting with abstract metering for multicore systemscitations
- 2015Increasing multicore system efficiency through intelligent bandwidth shiftingcitations
- 2014DReAM: Per-Task DRAM energy metering in multicore systemscitations
- 2014Per-task Energy Accounting in Computing Systemscitations
- 2014Analyzing the efficiency of l1 caches for reliable hybrid-voltage operation using edc codescitations
- 2014Hybrid cache designs for reliable hybrid high and ultra-low voltage operationcitations
- 2013APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operationcitations
- 2013Efficient cache architectures for reliable hybrid voltage operation using EDC codes
- 2013Hardware Support for Accurate Per-Task Energy Metering in Multicore Systemscitations
- 2013Fair CPU time accounting in CMP+SMT processorscitations
- 2013Thread assignment of multithreaded network applications in multicore/multithreaded processorscitations
- 2013SMT malleability in IBM POWER5 and POWER6 processorscitations
- 2012ADAM: An efficient data management mechanism for hybrid high and ultra-low voltage operation cachescitations
- 2012CPU accounting for multicore processorscitations
- 2012Optimal task assignment in multithreaded processors: A statistical approachcitations
- 2011RVC: A mechanism for time-analyzable real-time processors with faulty cachescitations
- 2011RVC-based time-predictable faulty caches for safety-critical systemscitations
- 2011Hybrid high-performance low-power and ultra-low energy reliable cachescitations
- 2011Dynamic cache partitioning based on the MLP of cache missescitations
- 2011IA3: An interference aware allocation algorithm for multicore hard real-time systemscitations
- 2011Characterizing power and temperature behavior of POWER6-based systemcitations
- 2011Energy-aware accounting and billing in large-scale computing facilitiescitations
- 2011A quantitative analysis of OS noisecitations
- 2010Power and performance aware reconfigurable cache for CMPscitations
- 2010On the problem of evaluating the performance of multiprogrammed workloadscitations
- 2010Trends and techniques for energy efficient architecturescitations
- 2010Adapting cache partitioning algorithms to pseudo-LRU replacement policiescitations
- 2010Load balancing using dynamic cache allocationcitations
- 2010Power and thermal characterization of POWER6 systemcitations
- 2010Thread to strand binding of parallel network applications in massive multi-threaded systemscitations
- 2009Thread to core assignment in SMT on-chip multiprocessorscitations
- 2009CPU accounting in CMP processorscitations
- 2009FlexDCP: A QoS framework for CMP architecturescitations
- 2009An analyzable memory controller for hard real-time CMPscitations
- 2009ITCA: Inter-task conflict-aware CPU accounting for CMPscitations
- 2009Characterizing the resource-sharing levels in the UltraSPARC T2 processorcitations
- 2009Hardware support for WCET analysis of hard real-time multicore systemscitations
- 2008Selection of the register file size and the resource allocation policy on SMT processorscitations
- 2008Soft real-time scheduling on SMT processors with explicit resource allocationcitations
- 2008Evolutionary system for prediction and optimization of hardware architecture performancecitations
- 2008Multicore resource managementcitations
- 2008A dynamic scheduler for balancing HPC applicationscitations
- 2008Software-controlled priority characterization of POWERS processorcitations
- 2008Measuring operating system overhead on CMT processorscitations
- 2008MFLUSH: Handling long-latency loads in SMT on-chip multiprocessors
- 2008MLP-aware dynamic cache partitioningcitations
- 2008A two-level load/store queue based on execution localitycitations
- 2008Architecture performance prediction using evolutionary artificial neural networkscitations
- 2008Balancing HPC applications through smart allocation of resources in MT processorscitations
- 2007A flexible heterogeneous multi-core architecture
- 2007Measuring the performance of multithreaded processors
- 2007MLP-aware dynamic cache partitioning
- 2007On the problem of minimizing workload execution time in SMT processorscitations
- 2007Explaining dynamic Cache Partitioning speed upscitations
- 2007Online prediction of applications cache utilitycitations
- 2006Predictable performance in SMT processors: Synergy between the OS and SMTscitations
- 2005Architectural Support for Real-Time Task Scheduling in SMT
- 2004Predictable performance in SMT processors
- 2004Implicit vs. explicit resource allocation in SMT processorscitations
- 2004Optimising long-latency-load-aware fetch policies for SMT processors
- 2004DCache warn: An I-Fetch policy to increase SMT efficiency
- 2004Feasibility of QoS for SMT
- 2004Dynamically controlled resource allocation in SMT processors
- 2004QoS for high-performance SMT processors in embedded systemscitations
- 2003Improving memory latency aware fetch policies for SMT processors
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